Metal-Oxide-Semiconductor (MOS) is the primary technology for ultra large-scale integrated (ULSI) circuits. To gain performance advantages, scaling down the size of MOS devices has been the principal focus of the microelectronics industry over the last two decades.
The conventional process of manufacturing MOS devices involves doping a silicon substrate and forming a gate oxide on the substrate followed by a deposition of polysilicon. A photolithographic process is used to etch the polysilicon to form the device gate. As device sizes are scaled down, the gate width, source junctions and drain junctions have to scale down. As the gate width reduces, the channel length between the source and drain is shortened. The shortening in channel length has led to several severe problems.
One of the problems associated with shortened channel length is the so-called "hot carrier effect". As the channel length is shortened, it causes a saturated condition that increases the maximum energy on the drain side of the MOS device. The high energy causes electrons in the channel region to become "hot". The electron generally becomes hot in the vicinity of the drain edge of the channel where the energy arises. Hot electrons can degrade device performance and cause breakdown of the device. Moreover, the hot electrons can overcome the potential energy barrier between the silicon substrate and the silicon dioxide layer overlying the substrate, which causes hot electrons to be injected into the gate oxide.
Problems arising from hot carrier injections into the gate oxide include generation of a gate current and generation of a positive trapped charge which can be permanently increase the threshold voltage of the MOS device. These problems are manifested as an undesirable decrease in saturation current, decrease of the transconductance, and a continual reduction in device performance caused by trapped charge accumulation. Thus, hot carrier effects cause unacceptable performance degradation in MOS devices built with conventional drain structures when channel lengths are short.
To try to remedy these problems, alternative drain structures such as lightly doped drain (LDD) structures have been developed. Lightly doped drain structures act as parasitic resistors and absorb some of the energy into the drain and thus reduce maximum energy in the channel region. This reduction in energy reduces the formation of hot electrons.
In most typical LDD structures, sources/drains are formed by two implants with dopants. One implant is self-aligned to the polysilicon gates to form shallow source/drain extension junctions or the lightly doped source/drain regions. Oxide or oxynitride spacers then would be formed around the polysilicon gate. With the shallow drain extension junctions protected by the spacers, a second implant with heavier dose is self-aligned to the oxide spacers around polysilicon gates to form deep source/drain junctions. There would then be a rapid thermal anneal (RTA) for the source/drain junctions to enhance the diffusion of the dopants implanted in the deep source/drain junctions so as to optimize the device performance. The purpose of the first implant is to form a LDD at the edge near the channel. In a LDD structure, almost the entire voltage drop occurs across the lightly doped drain region. The second implant with heavier dose forms low resistance deep drain junctions, which are coupled to the LDD structures. Since the second implant is spaced from the channel by the spacers, the resulting drain junction adjacent the light doped drain region can be made deeper without impacting device operation. The increase junction depth lowers the sheet resistance and the contact resistance of the drain.
Further improvements in transistor reliability and performances for exceeding smaller devices are achieved by a transistor having LDD structures only at the drain region (asymmetric LDD structures). Parasitic resistance due to the LDD structure at the source region of a transistor causes a decrease in drain current as well as a greater power dissipation for a constant supply voltage. The reduction in drain current is due to the effective gate voltage drop from self-biased negative feedback. At the drain region of the transistor, the drain region parasitic resistance does not appreciably affect drain current when the transistor is operating in the saturation region. Therefore, to achieve high-performance MOS transistor operation, it is known to form LDD structures only at the drain regions but not at the source regions.
While forming LDD structures only at the drain regions may improve transistor performance, it requires the use of an additional photolithographic masking process using implant masks to prevent ion implantation of the source regions (yet to be formed) during the first implant. The additional photolithographic process adversely increases cycle time and process complexity and also introduce particles and defects, resulting in an increase in cost and yield loss. Accordingly, forming LDD structures at both the source and drain regions remain to be the preferred alternative.
One significant problem with the LDD structures is the formation of parasitic capacitors. These parasitic capacitors are formed due to the diffusion of dopants from the LDD towards the channel regions underneath the polysilicon gates as a result of rapid thermal anneal and other heating processes in the manufacturing of the transistors. These parasitic capacitors are highly undesirable because they slow down the switching speed of the transistors. The adverse speed impact increases disproportionately with shortened channels. Basically, the parasitic capacitance due to LDD structures as a percentage of the total transistor capacitance is higher for sub-0.18 micron transistors than it is for a 0.18 micron transistor and even worse for a sub-0.13 transistor, making the adverse speed impact much more significant in smaller transistors.
As the push to ever-higher performance semiconductor devices continues, smaller gate width is the remedy of choice. Because the desired gate width is smaller than the smallest gate width current lithography light sources can provide, alternative methods have been developed to reduce the gate width. One such technique is trimming the polysilicon gate photoresist masks to smaller dimensions by using an anisotropic oxygen plasma process prior to the gate etch begins. Subsequently, the polysilicon gates are formed using a conventional etching process. The polysilicon gates thus formed replicate the dimensions of the trimmed photoresist masks, resulting in smaller gate widths. As explained above, however, the speed performance of these transistors is still impaired because of the significant increase in parasitic capacitance due to LDD structures
The conventional approaches to reduce parasitic capacitance have been to reduce LDD implant dosage or scaling down the operating voltage. However, these approaches also degrade the performance of the transistors.
A method to reduce the parasitic capacitance due to LDD structures without compromising transistor performance has long been sought but has eluded those skilled in the art.